The input to the half-adder is digits from the first column, A o = 1 and B o = 1 the input to the adjacent full adder is a carry C o = 1 from the half-adder and digits A 1 = 1 and B 1 = 1 from the second column, which gives C 1 = 1 and S 1 as the output of the first full adder. Note that for the numbers chosen the addition of each column produces a carry of 1. 7.14b shows the resultant sum 1110 of the addition of the two numbers A and B.
All other positions require a full adder. As a carry input is not needed in the least significant column ( A o, B o), a half-adder is sufficient for this position. If, for example, two binary numbers A = 111 and B = 111 are to be added, we would need three adder circuits in parallel, as shown in Fig. Such an adder is called a full adder and consists of two half-adders and an OR gate in the arrangement shown in Fig. Compare delay and size with a 2-bit carry-ripple adder implemented with (radix-2) full-adders (use average delays).įor general addition an adder is needed that can also handle the carry input. 2.3ĭesign a radix-4 full adder using the CMOS family of gates shown in Table 2.4.
L load on the gate output * different characteristics for each input + XNOR same characteristics as XOR for full-adder characteristics see Table 2.2 2.2ĭetermine the delay of a 32-bit adder using the full-adder characteristics of Table 2.4 (average delays).